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Soft Error Rate Assessment Studies of Space borne Computer

Volume 12, Number 5, September 2016 - Paper 3 - pp. 423-432

FAISAL MUSTAFA SAJJADE1, NEERAJ KUMAR GOYAL2, RAVINDRA MOOGINA1 and VARAPRASAD BKSVL1

1. ISRO Satellite Centre, Bangalore, INDIA
2. Reliability Engineering Centre, IIT Kharagpur, INDIA

(Received on April 23, 2016, revised on August 16, 2016)

Abstract:

Space borne computer (SBC), critical system of a spacecraft, comprises of CMOS Microprocessor, FPGA and memories. These devices are sensitive to single event upset (SEU) when exposed to space radiation environment and occurrence of SEU in on-board computer may hamper the spacecraft operations and affects the availability. Design hardening techniques such as triple modular redundancy (TMR), error detection and correction (EDAC), scrubbing is generally employed in the SBC to mitigate the SEU effect on system performance and soft error rate (SER). Many times hardening of whole design of SBC against SEU may not be possible due to various reasons. Therefore, a systematic approach is needed for hardening of selected design modules and allowing un-protected design modules for flight usage without compromising targeted availability requirement of SBC. Paper present methodology for soft error rate (SER) estimation, hardening of selected logic blocks and assessment of availability of SBC.

 

References: 16

 

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