Username   Password       Forgot your password?  Forgot your username? 


UCM: A Novel Approach for Delay Optimization

Volume 15, Number 4, April 2019, pp. 1190-1198
DOI: 10.23940/ijpe.19.04.p14.11901198

Rajkumar Sarmaa, Cherry Bhargavaa, Sandeep Dhariwalb, and Shruti Jainc

aSchool of Electronics and Electrical Engineering, Lovely Professional University, Phagwara, Punjab, 144411, India
bAlliance College of Engineering and Design, Alliance University, Bengaluru, Karnataka, 562106, India
cDepartment of Electronics and Communication Engineering, Jaypee University of Information Technology, Waknaghat, Himachal Pradesh, 173234, India


(Submitted on December 25, 2018; Revised on December 27, 2018; Accepted on April 15, 2019)


In the era of digital signal processing, such as graphics and computation systems, multiplication is one of the prime operations. A multiplier is a key component in any kind of digital system such as Multiply-Accumulate (MAC) unit, various FFT algorithms, etc. The efficiency of a multiplier is mainly dependent upon the speed of operation and power dissipation of the circuit along with the complexity level of the multiplier. This paper is based on Universal Compressor based Multiplier (UCM), which yields a high-speed operation with comparative power dissipation; hence, the enhanced performance is reported. The novel design of UCM is analyzed using Cadence Spectre tool in 90nm CMOS technology. Finally, the UCM is implemented using Nexys-4 Artix-7 FPGA board. The novel design of UCM has demonstrated significant improvement in terms of delay, which is explored in this paper.

References: 18

    1. M. Liao, C. Su, C. Chang, and A. C. Wu, “A Carry-Select-Adder Optimization Technique for High-Performance Booth-Encoded Wallace-Tree Multipliers,” IEEE International Symposium on Circuits and Systems, ISCAS 2002, 2002
    2. D. Guevorkian, A. Launiainen, V. Lappalainen, P. Liuha, and K. Punkka, “A Method for Designing High-Radix Multiplier-based Processing Units for Multimedia Applications,” IEEE Transactions on Circuits and Systems for Video Technology, Vol. 15, No. 5, pp. 716-725, 2005
    3. N. Itoh, Y. Naemura, H. Makino, Y. Nakase, T. Yoshihara, and Y. Horiba, “A 600-MHz 54 54-bit Multiplier with Rectangular-Styled Wallace Tree,” IEEE Journal of Solid-State Circuits, Vol. 36, No. 2, pp. 249-257, 2001
    4. K. B. Jaiswal, N. Kumar, P. Seshadri, and G. Lakshminarayanan, “Low Power Wallace Tree Multiplier using Modified Full Adder,” in Proceedings of the 3rd International Conference on Signal Processing, Communication and Networking (ICSCN), 2015
    5. I. Kataeva, H. Engseth, and A. Kidiyarova-Shevchenko, “Scalable Matrix Multiplication With Hybrid CMOS-RSFQ Digital Signal Processor,” IEEE Transactions on Applied Superconductivity, Vol. 17, No. 2, pp. 486-489, 2007
    6. S. Khan, S. Kakde, and Y. Suryawanshi, “VLSI Implementation of Reduced Complexity Wallace Multiplier using Energy Efficient CMOS Full Adder,” in Proceedings of the IEEE International Conference on Computational Intelligence and Computing Research, 2013
    7. R. D. Kshirsagar, E. V. Aishwarya, A. S. Vishwanath, and P. Jayakrishnan, “Implementation of Pipelined Booth Encoded Wallace Tree Multiplier Architecture,” in Proceedings of the International Conference on Communication and Green Computing Conservation of Energy (ICGCE), 2013
    8. T. Y. Kuo and J. S. Wang, “A Low-Voltage Latch-Adder based Tree Multiplier,” in Proceedings of the IEEE International Symposium on Circuits and Systems, Seattle, WA, 2008
    9. X. V. Luu, T. T. Hoang, T. T. Bui, and A. V. Dinh-Duc, “A High-Speed Unsigned 32-bit Multiplier based on Booth encoder and Wallace-tree Modifications,” in Proceedings of the International Conference on Advanced Technologies for Communications (ATC'14), 2014
    10. M. Nachtigal, H. Thapliyal, and N. Ranganathan, “Design of a Reversible Single Precision Floating Point Multiplier based on Operand Decomposition,” in Proceedings of the 10th IEEE conference on Nanotechnology, Kintex, Korea, 2010
    11. T. Onomi, K. Yanagisawa, M. Seki, and K. Nakajima, “Phase-Mode Pipelined Parallel Multiplier,” IEEE Transactions on Applied Superconductivity, Vol. 11, No. 1, pp. 541-544, 2001
    12. C. Paradhasaradhi, M. Prashanthi, and N. Vivek, “Modified Wallace Tree Multiplier using Efficient Square-Root Carry Select Adder,” in Proceedings of the International Conference on Green Computing Communication and Electrical Engineering (ICGCCEE), Coimbatore, 2014
    13. M. J. Rao and S. Dubey, “A High Speed and Area Efficient Booth Recoded Wallace Tree Multiplier for fast Arithmetic Circuits,” in Proceedings of the Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PRIMEASIA), BITS Pilani, Hyderabad, 2012
    14. B. M. Reddy, H. N. Sheshagiri, B. R. Vijaykumar, and S. Shanthala, “Implementation of Low Power 8-bit Multiplier using Gate Diffusion Input Logic,” in Proceedings of the 17th IEEE International Conference on Computational Science and Engineering, 2014
    15. A. K. Singh, B. P. De, and S. Maity, “Design and Comparison of Multipliers using Different Logic Styles,” International Journal of Soft Computing and Engineering (IJSCE), Vol. 2, No. 2, pp. 374-379, 2012
    16. L. Sousa, “Algorithm for Modulo (2n+1) Multiplication,” Electronics Letters, pp. 752-754, May 2013
    17. C. S. Wallace, “A Suggestion for a Fast Multiplier,” IEEE Transactions on Electronic Computers, pp. 14-17, 1964
    18. Q. Yi and H. Jing, “An Improved Design Method for Multi-bits Reused Booth Multiplier,” in Proceedings of the 4th International Conference on Computer Science and Education, 2009





    Please note : You will need Adobe Acrobat viewer to view the full articles.Get Free Adobe Reader

    This site uses encryption for transmitting your passwords.