Program Disturb Research and Error Avoidance Algorithm Design of 3D-TLC NAND Flash Memory

doi:10.23940/ijpe.18.08.p4.16851694

Abstract

Abstract:

This paper focuses on finding, settling and reducing the program disturb error of 3D-TLC NAND flash memory. Experimental analysis of the FPGA test platform determines characteristics of the program disturb error. The program disturb error makes the state shift rate of storage cells lose balance. MSB, CSB and LSB pages have unbalanced bit error ratio and bit error rate distribution. The page program disturb bit error is unbalanced as the number of program/erase cycles changes. Based on the experimental results of the error rate imbalance, an error avoidance algorithm is designed, which can shift the data state that is subject to program disturb to one that is not vulnerable to program disturb. The test results show that the algorithm can reduce the error rate of program disturb by 20% to 90%. In this sense, the program disturb error phenomenon found and error avoidance algorithm designed in this paper are helpful for improving the reliability of 3D-TLC NAND flash memory.

Submitted on April 30, 2018; Revised on June 8, 2018; Accepted on July 15, 2018
References: 20

Xiaoshan Yang, Ligu Zhu, Qicong Zhang, Meng Zhang, Fei Wu, and Wei Zhang. Program Disturb Research and Error Avoidance Algorithm Design of 3D-TLC NAND Flash Memory [J]. Int J Performability Eng, 2018, 14(8): 1685-1694.

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