A Cache Consistency Protocol with Improved Architecture

doi:10.23940/ijpe.18.01.p19.178185

Abstract

Abstract:

With the technical innovation of microprocessors, the application of cache memory prevents the main memory from limiting the development of microprocessors. However, the introduction of Cache also brings the cache coherence problem while the microprocessor performance is being improved. Based on this problem, this paper designs an improved CMP architecture model and proposes a new Cache Coherence Protocol Based on Virtual Bus (CCPBVB). Firstly, the D-Cache virtual bus is added to the architecture to realize the point-to-point consistency transaction transmission, avoiding the bus idle phenomenon caused by the polling query method that the broadcast consistency transaction must follow, while also improving the effective utilization rate of the bus. Then, in order to reduce the access delay caused by the ping-pong phenomenon in the cache memory, a protocol is designed to improve the C hit rate, which combines the write invalid strategy and write update strategy between the private cache to reduce the delay time of the system. The experimental results show that the proposed protocol not only improves the bus utilization, but also reduces the C access delay.

Submitted on October 22, 2017; Revised on November 19, 2017; Accepted on December 21, 2017
References: 16

Qiao Tian, Jingmei Li, Shuo Zhao, Fangyuan Zheng, and Jiaxiang Wang. A Cache Consistency Protocol with Improved Architecture [J]. Int J Performability Eng, 2018, 14(1): 178-185.

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References 0

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