Implementation of Normal Urdhva Tiryakbhayam Multiplier in VLSI

doi:10.23940/ijpe.21.06.p3.511518

Abstract

Abstract: Presently, low-power VLSI configuration is pulling in all the electronic gadgets since power turned into a significant basis in planning. Today, practically the entirety of the electronic gadgets is being utilized in battery reinforcement for compactness and comfort. This low force utilization will likewise help in decreasing heat dissipation in such electronic gadgets bringing about wide and long use. Multipliers are utilized generally in advanced sign handling applications. An effective plan of the multiplier has been planned. Since multipliers are an essential part of a large portion of electronic gadgets. A mix of the multiplier is dependent on the specific boundaries like area, speed, and power in which VLSI configuration should be concentrated. In this paper, the normal VLSI multiplier architecture has been implemented for 2×2, 4×4, 8×8, 16×16, and 32×32 bits using a conventional logic gate. The performance is evaluated by the power, delay, and area of each multiplier circuit design. Simulations are carried out for series target boards and results are compared with multipliers implemented with other VLSI multiplier architecture.

Key words: VLSI, Vedic multiplier, Urdhva Tiryakbhayam, CMOS, power, delay, area

V. Nandhini and K. Sambath. Implementation of Normal Urdhva Tiryakbhayam Multiplier in VLSI [J]. Int J Performability Eng, 2021, 17(6): 511-518.

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