Hybrid GDI PTL Full Adder: A Proposed Design for Low Power Applications

doi:10.23940/ijpe.22.01.p3.2229

Abstract

Abstract: Low power devices have always been important in all electronics and computer devices. In this paper, a proposed design has been implemented for the full adder circuit with significant modifications in the existing hybrid GDI (Gate Diffusion Input) based full adder. All the results are implemented using CADENCE tool at 45nm scale and 0.4V. Existing hybrid GDI based adder design delivers 7.135x10^-9 watt power dissipation. The proposed hybrid GDI-PTL design delivers a significant reduction in power dissipation equal to 6.70x10^-9watt. Further, this power dissipation has been reduced to 6.55x10^-9 watt by using high Vth (threshold voltage) PMOS transistor in the proposed hybrid GDI-PTL design for one-bit full adder.

Key words: GDI (gate diffusion input), PTL (pass transistor logic), Vth (threshold voltage), CMOS, low power dissipation

Sandeep Dhariwal, Reeba Korah, Ravi Shankar Mishra, and Gaurav Kumar. Hybrid GDI PTL Full Adder: A Proposed Design for Low Power Applications [J]. Int J Performability Eng, 2022, 18(1): 22-29.

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References

1. Alioto M.ed. Enabling the Internet of Things: From Integrated Circuits to Integrated Systems. Springer, 2017.
2. Singh N., Kaur M., Singh A., andJain P.An Efficient Full Adder Design using Different Logic Styles. International Journal of Computer Applications, vol. 98, no. 21, 2014.
3. Shams A.M., Darwish T.K., andBayoumi M.A.Performance Analysis of Low-power 1-bit CMOS Full Adder cells. IEEE transactions on very large scale integration (VLSI) systems, vol. 10, no. 1, pp. 20-29, 2002.
4. Rabaey J.M., Chandrakasan A.P., andNikolić B.Digital integrated circuits: a design perspective (Vol. 7). Upper Saddle River, NJ: Pearson education, 2003.
5. Weste, N.H. and Harris, D.CMOS VLSI design: a circuits and systems perspective. Pearson Education India, 2015.
6. Navi K., Foroutan V., Azghadi M.R., Maeen M., Ebrahimpour M., Kaveh M., andKavehei O.A Novel Low-power Full-adder Cell with new Technique in Designing Logical Gates based on Static CMOS Inverter. Microelectronics Journal, vol. 40, no. 10, pp. 1441-1448, 2009.
7. Navi K., Maeen M., Foroutan V., Timarchi S. and Kavehei O.A Novel Low-power Full-adder Cell for low Voltage. Integration, vol. 42, no. 4, pp. 457-467, 2009.
8. Radhakrishnan D.Low-voltage Low-power CMOS Full Adder. IEE Proceedings-Circuits, Devices and Systems, vol. 148, no. 1, pp. 19-24, 2001.
9. Zimmermann, R. and Fichtner, W.Low-power Logic Styles: CMOS Versus Pass-transistor Logic. IEEE journal of solid-state circuits, vol. 32, no. 7, pp. 1079-1090, 1997.
10. Alioto M.,Di Cataldo, G., and Palumbo, G. Mixed Full Adder Topologies for High-performance Low-power Arithmetic Circuits. Microelectronics Journal, vol. 38, no. 1, pp. 130-139, 2007.
11. Zhang, M., Gu, J., and Chang, C.H. A Novel Hybrid Pass Logic with Static CMOS Output Drive Full-adder Cell. In Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS'03, IEEE, vol. 5, 2003.
12. Shubin V.V.New CMOS Circuit Implementation of a One-bit Full-adder Cell. Russian Microelectronics, vol. 40, no. 2, pp. 119-127, 2011.
13. Morgenshtein, A., Fish, A. and Wagner, I.A.Gate-diffusion Input (GDI): a Power-efficient Method for Digital Combinatorial Circuits. IEEE transactions on very large scale integration (VLSI) systems, vol. 10, no. 5, pp. 566-581, 2002.
14. Sanapala, K. and Sakthivel, R.Analysis of GDI Logic for Minimum Energy Optimal Supply Voltage. In2017 International conference on Microelectronic Devices, Circuits and Systems (ICMDCS), IEEE, pp. 1-3, 2017.
15. Lee, P.M., Hsu, C.H. and Hung, Y.H.Novel 10-T Full Adders Realized by GDI Structure. In2007 International Symposium on Integrated Circuits, IEEE, pp. 115-118, 2007.

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